Description
64 Analog inputs with dedicated 18-Bit SAR ADC per Channel
Simultaneous sampling of all inputs; Minimum Data Skew
Sampling Rates to 750 KSPS per channel (48 MSPS aggregate rate)
Continuous, Burst and Single-Sample Clocking Modes
Software and I/O pinout compatibility with the 16AI64SSA/C
Selectable Differential Processing Simulates Differential Operation of Channel Pairs
Input Ranges software-selectable as ±10V, ±5V, 0 to +5V or 0 to +10V
Hardware Sync I/O for Multiboard Operation
FIFO buffer provides 256 K-Sample data capacity at 18 bits; 512K at 16 bits with data packing.
A software-selectable low-latency configuration provides 64 registers that duplicate the last sample from all A/D converters
2-Channel DMA Engine
Sampling and burst triggering controlled by internal rate generators, or by direct software control, or externally
On-demand internal autocalibration of all channels
Completely software-configurable; No field jumpers
D32; 66MHz, 33MHz PCI compatibility, with universal 5V/3.3V Signaling
Internal Sync/Clock I/O connector provides behind-panel access to clock and sync signals
PMC version protected with integral EMI shield over analog components
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